 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| v cc seg 6 seg 7 v l2 v l1 p5 7 /adt p5 6 / p4 7 /s rdy p4 6 /s clk p4 5 / p4 4 /r x d p4 3 /int 1 p4 2 /int 0 p5 0 /int 2 p5 4 /cntr 0 p5 2 /rtp 0 p5 3 /rtp 1 p5 1 /int 3 p5 5 /cntr 1 p6 7 /an 7 p4 1 / f p4 0 x in x out v ss p2 7 p2 6 p2 5 p2 4 p2 3 p2 2 p2 1 p2 0 reset p7 0 /x cout p7 1 /x cin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 m38223m4-xxxfp 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 43 42 41 44 seg 5 seg 3 seg 4 seg 2 seg 1 seg 0 v ref av ss com 2 com 3 com 1 com 0 v l3 p6 6 /an 6 p6 5 /an 5 p6 4 /an 4 p6 3 /an 3 p6 2 /an 2 p6 1 /an 1 p6 0 /an 0 t out t x d seg 8 seg 9 seg 10 seg 11 p3 4 /seg 12 p3 5 /seg 13 p3 6 /seg 14 p3 7 /seg 15 p0 0 /seg 16 p0 1 /seg 17 p0 2 /seg 18 p0 3 /seg 19 p0 4 /seg 20 p0 5 /seg 21 p0 6 /seg 22 p0 7 /seg 23 p1 0 /seg 24 p1 1 /seg 25 p1 2 /seg 26 p1 3 /seg 27 p1 4 /seg 28 p1 5 /seg 29 p1 6 /seg 30 p1 7 /seg 31 3822 group pin configuration (top view) package type : 80p6n-a 80-pin plastic-molded qfp description the 3822 group is the 8-bit microcomputer based on the 740 fam- ily core technology. the 3822 group has the lcd drive control circuit an 8-channel a- d converter, and a serial i/o as additional functions. the various microcomputers in the 3822 group include variations of internal memory size and packaging. for details, refer to the section on part numbering. for details on availability of microcomputers in the 3822 group, re- fer to the section on group expansion. features ? basic machine-language instructions ....................................... 71 ? the minimum instruction execution time ............................ 0.5 m s (at 8mhz oscillation frequency) ? memory size rom .................................................................. 4 k to 32 k bytes ram ................................................................. 192 to 1024 bytes ? programmable input/output ports ............................................. 49 ? software pull-up/pull-down resistors (ports p0-p7 except port p4 0 ) ? interrupts .................................................. 17 sources, 16 vectors (includes key input interrupt) ? timers ........................................................... 8-bit 5 3, 16-bit 5 2 ? serial i/o1 ..................... 8-bit 5 1 (uart or clock-synchronized) ? serial i/o2 ........................................................ 8-bit 5 8 channels ? lcd drive control circuit bias ................................................................................... 1/2, 1/3 duty ............................................................................ 1/2, 1/3, 1/4 common output .......................................................................... 4 segment output ......................................................................... 32 ? 2 clock generating circuit clock (x in -x out ) .................................. internal feedback resistor sub-clock (x cin -x cout ) .......... without internal feedback resistor (connect to external ceramic resonator or quartz-crystal oscillator) ? power source voltage in high-speed mode .................................................... 4.0 to 5.5 v (at 8mhz oscillation frequency and high-speed selected) in middle-speed mode ................................................ 2.5 to 5.5 v (at 8mhz oscillation frequency and middle-speed selected) in low-speed mode ...................................................... 2.5 to 5.5 v (extended operating temperature version: 3.0 v to 5.5 v) ? power dissipation in high-speed mode ........................................................... 32 mw (at 8 mhz oscillation frequency) in low-speed mode .............................................................. 45 m w (at 32 khz oscillation frequency, at 3 v power source voltage) ? operating temperature range ................................... C 20 to 85 c (extended operating temperature version: C40 to 85 c) applications camera, household appliances, consumer electronics, etc. mitsubishi microcomputers single-chip 8-bit cmos microcomputer
2 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3822 group pin configuration (top view) package type : 80p6s-a/80p6d-a 80-pin plastic-molded qfp m38223m4-xxxgp m38223m4-xxxhp p4 1 / f p4 0 x in x out v ss p2 7 p2 6 p2 5 p2 4 p2 3 p2 2 p2 1 p2 0 reset p7 0 /x cout p7 1 /x cin v cc seg 6 seg 7 seg 5 seg 3 seg 4 seg 2 seg 1 seg 0 v ref av ss com 2 com 3 com 1 com 0 v l3 v l2 v l1 p5 7 /adt p4 7 /s rdy p4 6 /s clk p4 4 /r x d p4 3 /int 1 p4 2 /int 0 p5 0 /int 2 p5 4 /cntr 0 p5 2 /rtp 0 p5 3 /rtp 1 p5 1 /int 3 p5 5 /cntr 1 p6 7 /an 7 p6 6 /an 6 p6 5 /an 5 p6 4 /an 4 p6 3 /an 3 p6 2 /an 2 p6 1 /an 1 p6 0 /an 0 p5 6 / t out p4 5 / t x d seg 8 seg 9 seg 10 seg 11 p3 4 /seg 12 p3 5 /seg 13 p3 6 /seg 14 p3 7 /seg 15 p0 0 /seg 16 p0 1 /seg 17 p0 2 /seg 18 p0 3 /seg 19 p0 4 /seg 20 p0 5 /seg 21 p0 6 /seg 22 p0 7 /seg 23 p1 0 /seg 24 p1 1 /seg 25 p1 2 /seg 26 p1 3 /seg 27 p1 4 /seg 28 p1 5 /seg 29 p1 6 /seg 30 p1 7 /seg 31 41 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 43 42 44 21 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 23 22 24 80 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 78 79 77 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18 19 17 3 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3822 group functional block diagram (package : 80p6s-a) adt cntr 0 ,cntr 1 t out cpu a x y s pc h pc l ps rom p7(2) si/o(8) v l1 v l2 v l3 com 0 com 1 com 2 com 3 x cin x cout 28 f lcd drive control circuit ram lcd display ram (16 bytes) timer x(16) timer y(16) timer 1(8) timer 2(8) timer 3(8) data bus clock generating circuit clock input x in clock output x out x cout sub- clock output x cin sub- clock input v cc reset input (5 v) reset key-on wake up real time port function int 0 , int 1 a-d converter(8) rtp 0 ,rtp 1 29 25 71 30 v ss (0 v) 80 79 78 77 76 75 74 70 69 68 67 66 65 64 63 62 61 60 59 seg 11 seg 1 seg 2 seg 3 seg 4 seg 5 seg 6 seg 7 seg 8 seg 9 seg 10 seg 0 47 54 i/o port p0 p0(8) 53 52 51 50 49 48 39 46 i/o port p1 p1(8) 45 44 43 42 41 40 31 38 i/o port p2 p2(8) 37 36 35 34 33 32 input port p3 p3(8) 58 57 56 55 f 17 24 i/o port p4 p4(8) 23 22 21 20 19 18 9 16 i/o port p5 p5(8) 15 14 13 12 11 10 int 2 , int 3 73 72 v ref av ss (0 v) 1 8 i/o port p6 p6(8) 7 6 5 4 3 2 27 26 i/o port p7 4 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3822 group function ? apply voltage of 2.5 v to 5.5 v to v cc , and 0 v to v ss . ? reference voltage input pin for a-d converter. ? gnd input pin for a-d converter. ? connect to v ss . ?reset input pin for active l ? input and output pins for the main clock generating circuit. ? feedback resistor is built in between x in pin and x out pin. ? connect a ceramic resonator or a quartz-crystal oscillator between the x in and x out pins to set the oscillation frequency. ? if an external clock is used, connect the clock source to the x in pin and leave the x out pin open. ? this clock is used as the oscillating source of system clock. ? input 0 v l1 v l2 v l3 v cc voltage ? input 0 C v l3 voltage to lcd ? lcd common output pins ? com 2 and com 3 are not used at 1/2 duty ratio. ? com 3 is not used at 1/3 duty ratio. ? lcd segment output pins ? 8-bit i/o port ? cmos compatible input level ? cmos 3-state output structure ? i/o direction register allows each port to be individually programmed as either input or output. ? pull-down control is enabled. ? 8-bit i/o port ? cmos compatible input level ? cmos 3-state output structure ? i/o direction register allows each pin to be individually programmed as either input or output. ? pull-up control is enabled. ? 4-bit input port ? cmos compatible input level ? pull-down control is enabled. ? 1-bit input pin ? cmos compatible input level ? 7-bit i/o port ? cmos compatible input level ? cmos 3-state output structure ? i/o direction register allows each pin to be individually programmed as either input or output. ? pull-up control is enabled. ? lcd segment pins ? key input (key-on wake up) interrupt input pins ? lcd segment pins ? f clock output pin ? interrupt input pins ? serial i/o1 function pins pin v cc , v ss v ref av ss reset x in x out v l1 C v l3 com 0 C com 3 seg 0 C seg 11 p0 0 / seg 16 C p0 7 / seg 23 p1 0 /seg 24 C p1 7 / seg 31 p2 0 C p2 7 p3 0 / seg 12 C p3 7 / seg 15 p4 0 p4 1 / f p4 2 /int 0 , p4 3 /int 1 p4 4 /r x d, p4 5 /t x d, p4 6 /s clk, p4 7 /s rdy name power source analog reference voltage analog power source reset input clock input clock output lcd power source common output segment output i/o port p0 i/o port p1 i/o port p2 input port p3 input port p4 i/o port p4 function except a port function pin description 5 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3822 group function ? 8-bit i/o port ? cmos compatible input level ? cmos 3-state output structure ? i/o direction register allows each pin to be individually programmed as either input or output. ? pull-up control is enabled. ? 8-bit i/o port ? cmos compatible input level ? cmos 3-state output structure ? i/o direction register allows each pin to be individually programmed as either input or output. ? pull-up control is enabled. ? 2-bit i/o port ? cmos compatible input level ? cmos 3-state output structure ? i/o direction register allows each pin to be individually programmed as either input or output. ? pull-up control is enabled. pin p5 0 /int 2 , p5 1 /int 3 p5 2 /rtp 0 , p5 3 /rtp 1 p5 4 /cntr 0 , p5 5 /cntr 1 p5 6 /t out p5 7 /adt p6 0 /an 0 - p6 7 /an 7 p7 0 /x cout, p7 1 /x cin pin description name i/o port p5 i/o port p6 i/o port p7 function except a port function ? interrupt input pins ? real time port function pins ? timer function pins ? timer output pin ? a-d trigger input pin ? a-d conversion input pins ? sub-clock generating circuit i/o pins (connect a resonator. external clock cannot be used.) 6 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3822 group part numbering m3822 3 m 4 - xxx fp product rom/prom size 1 2 3 4 5 6 7 8 : 4096 bytes : 8192 bytes : 12288 bytes : 16384 bytes : 20480 bytes : 24576 bytes : 28672 bytes : 32768 bytes the first 128 bytes and the last 2 bytes of rom are reserved areas ; they cannot be used. memory type m e : mask rom version : eprom or one time prom version ram size 0 1 2 3 4 5 6 7 : 192 bytes : 256 bytes : 384 bytes : 512 bytes : 640 bytes : 768 bytes : 896 bytes : 1024 bytes package type fp gp hp fs rom number omitted in some types. normally, using hyphen when electrical characteristic, or division of quality identification code using alphanumeric character C : standard d : extended operating temperature version : 80p6n-a package : 80p6s-a package : 80p6d-a package : 80d0 package 7 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3822 group remarks mask rom version one t ime prom version one t ime prom version (blank) mask rom version one t ime prom version one t ime prom version (blank) mask rom version one t ime prom version one t ime prom version (blank) eprom version mask rom version product m38223m4-xxxfp m38223e4-xxxfp m38223e4fp m38223m4-xxxgp M38223E4-XXXGP m38223e4gp m38223m4-xxxhp m38223e4-xxxhp m38223e4hp m38223e4fs m38222m2-xxxfp m38222m2-xxxgp m38222m2-xxxhp group exp ansion mitsubishi plans to expand the 3822 group as follows: ( 1 ) support for mask rom, one t ime prom, and eprom versions ( 2 ) rom/prom size .......................................... 8 k to 16 k bytes ram size ....................................................... 384 to 512 bytes ( 3 ) packages 80p6n-a ............................. 0.8 mm-pitch plastic molded qfp 80p6s-a ........................... 0.65 mm-pitch plastic molded qfp 80p6d-a ............................. 0.5 mm-pitch plastic molded qfp 80d0 ................ 0.8 mm-pitch ceramic lcc (eprom version) memory expansion plan currently supported products are listed below . as of may 1996 ram size (bytes) 512 384 package 80p6n-a 80p6s-a 80p6d-a 80d0 80p6n-a 80p6s-a 80p6d-a 16384 (16254) (p) rom size (bytes) rom size for user in ( ) 8192 (8062) m38 223 m4/e4 mass product rom size (bytes) 32k 28k 24k 20k 16k 12k 8k 4k 192 256 384 512 640 768 896 1024 ra m size (bytes) m38 223 m2 mass product 8 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3822 group group exp ansion (extended opera ting tempera ture version) mitsubishi plans to expand the 3822 group (extended operatin g temperature version) as follows: ( 1 ) support for mask rom, one t ime prom, and eprom versions ( 2 ) rom size ............................................................ .... 16 k bytes ram size ............................................................ ...... 512 bytes (3) packages 80p6n-a ............................. 0.8 mm-pitch plastic molded qfp memory expansion plan currently supported products are listed below . ram size (bytes) 512 384 16384(16254) 8192(8062) remarks mask rom version mask rom version as of may 1996 package 80p6n-a 80p6s-a product m38223m4dxxxfp m38222m2dxxxgp rom size (bytes) rom size for user in ( ) products under development: the development schedule and spe cification may be revised without notice. m38 223 m4d under development rom size (bytes) 32k 28k 24k 20k 16k 12k 8k 4k 192 256 384 512 640 768 896 1024 ra m size (bytes) m38 222 m 2d mass product 9 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3822 group functional description central processing unit (cpu) the 3822 group uses the standard 740 family instruction set. refer to the table of 740 family addressing modes and machine inst ruc- tions or the series 740 10 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3822 group memory special function register (sfr) area the special function register area in the zero page contains con- trol registers such as i/o ports and timers. ram ram is used for data storage and for stack area of subroutine calls and interrupts. rom the first 128 bytes and the last 2 bytes of rom are reserved for device testing and the rest is user area for storing programs. interrupt vector area the interrupt vector area contains reset and interrupt vectors. zero page the 256 bytes from addresses 0000 16 to 00ff 16 are called the zero page area. the internal ram and the special function regis- ters (sfr) are allocated to this area. the zero page addressing mode can be used to specify memory and register addresses in the zero page area. access to this area with only 2 bytes is possible in the zero page addressing mode. special page the 256 bytes from addresses ff00 16 to ffff 16 are called the special page area. the special page addressing mode can be used to specify memory addresses in the special page area. ac- cess to this area with only 2 bytes is possible in the special page addressing mode. fig. 2 memory map diagram 192 256 384 512 640 768 896 1024 00ff 16 013f 16 01bf 16 023f 16 02bf 16 033f 16 03bf 16 043f 16 ram area ram size (bytes) address xxxx 16 4096 8192 12288 16384 20480 24576 28672 32768 f000 16 e000 16 d000 16 c000 16 b000 16 a000 16 9000 16 8000 16 f080 16 e080 16 d080 16 c080 16 b080 16 a080 16 9080 16 8080 16 rom area rom size (bytes) address yyyy 16 address zzzz 16 0100 16 0000 16 0040 16 0440 16 ff00 16 ffdc 16 fffe 16 ffff 16 xxxx 16 yyyy 16 zzzz 16 ram rom 0050 16 reserved area sfr area not used interrupt vector area reserved rom area (128 bytes) zero page special page lcd display ram area reserved rom area 11 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3822 group fig.3 memory map of special function register (sfr) 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002e 16 002f 16 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 0010 16 0011 16 0012 16 0013 16 0014 16 0015 16 0016 16 0017 16 0018 16 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 001f 16 port p0 (p0) port p0 direction register (p0d) port p1 (p1) port p1 direction register (p1d) port p2 (p2) port p2 direction register (p2d) port p3 (p3) port p4 (p4) port p4 direction register (p4d) port p5 (p5) port p5 direction register (p5d) port p6 (p6) port p6 direction register (p6d) port p7 (p7) port p7 direction register (p7d) serial i/o1 status register (sio1sts) serial i/o1 control register (sio1con) uart control register (uartcon) baud rate generator (brg) interrupt control register 2(icon2) timer 3 (t3) timer x mode register (txm) interrupt edge selection register (intedge) cpu mode register (cpum) interrupt request register 1(ireq1) interrupt request register 2(ireq2) interrupt control register 1(icon1) timer x (low) (txl) timer y (low) (tyl) timer 1 (t1) timer 2 (t2) timer x (high) (txh) timer y (high) (tyh) pull register a (pulla) pull register b (pullb) timer y mode register (tym) timer 123 mode register (t123m) f output control register (ckout) segment output enable register (seg) lcd mode register (lm) a-d control register (adcon) a-d conversion register (ad) transmit/receive buffer register(tb/rb) 12 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3822 group i/o ports direction registers (ports p2, p4 1 Cp4 7 , and p5Cp7) the 3822 group has 49 programmable i/o pins arranged in seven i/o ports (ports p0Cp2 and p4 1 Cp4 7 and p5Cp7). the i/o ports p2, p4 1 Cp4 7 , and p5Cp7 have direction registers which determine the input/output direction of each individual pin. each bit in a direc- tion register corresponds to one pin, each pin can be set to be in- put port or output port. when 0 is written to the bit corresponding to a pin, that pin be- comes an input pin. when 1 is written to that bit, that pin be- comes an output pin. if data is read from a pin set to output, the value of the port output latch is read, not the value of the pin itself. pins set to input are floating. if a pin set to input is written to, only the port output latch is written to and the pin remains floating. direction registers (ports p0 and p1) ports p0 and p1 have direction registers which determine the in- put /output direction of each individual port. each port in a direction register corresponds to one port, each port can be set to be input or output. when 0 is written to the bit 0 of a direction register, that port be- comes an input port. when 1 is written to that port, that port be- comes an output port. bits 1 to 7 of ports p0 and p1 direction registers are not used. ports p3 and p4 0 these ports are only for input. pull-up/pull-down control by setting the pull register a (address 0016 16 ) or the pull reg- ister b (address 0017 16 ), ports except for port p4 0 can control ei- ther pull-down or pull-up (pins that are shared with the segment output pins for lcd are pull-down; all other pins are pull-up) with a program. however, the contents of pull register a and pull register b do not affect ports programmed as the output ports. fig. 4 structure of pull register a and pull register b p0 0 Cp0 7 pull-down p1 0 Cp1 7 pull-down p2 0 Cp2 7 pull-up p3 0 Cp3 7 pull-down p7 0 , p7 1 pull-up not used (return 0 when read) pull register a (pulla : address 0016 16 ) b7 b0 p4 1 Cp4 3 pull-up p4 4 Cp4 7 pull-up p5 0 Cp5 3 pull-up p5 4 Cp5 7 pull-up p6 0 , p6 3 pull-up p6 4 Cp6 7 pull-up not used (return 0 when read) 0 : disable 1 : enable pull register b (pullb : address 0017 16 ) b7 b0 note : the contents of pull register a and pull register b do not affect ports programmed as the output ports. 13 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3822 group note : make sure that the input level at each pin is either 0 v or v cc during execution of the stp instruction. when an input level is at an intermediate potential, a current will flow from v cc to v ss through the input-stage gate. input/output input/output, individual ports input/output, individual ports input/output, individual bits input input/output, individual bits output related sfrs pull register a segment output enable register pull register a segment output enable register pull register a interrupt control register 2 pull register a segment output enable register pull register b f output control register pull register b interrupt edge selection register pull register b serial i/o control register serial i/o status register uart control register pull register b interrupt edge selection register pull register b timer x mode register pull register b timer x mode register pull register b timer y mode register pull register b timer 123 mode register pull register b a-d control register pull register a cpu mode register lcd mode register segment output enable register pin p0 0 /seg 16 C p0 7 /seg 23 p1 0 /seg 24 C p1 7 /seg 31 p2 0 C p2 7 p3 4 /seg 12 C p3 7 /seg 15 p4 0 p4 1 / f p4 2 /int 0 , p4 3 /int 1 p4 4 /r x d p4 5 /t x d p4 6 /s clk1 p4 7 /s rdy p5 0 /int 2 , p5 1 /int 3 p5 2 /rtp 0 , p5 3 /rtp 1 p5 4 /cntr 0 p5 5 /cntr 1 p5 6 /t out p5 7 /adt p6 0 /an 0 C p6 7 /an 7 p7 0 /x cout p7 1 /x cin com 0 -com 3 seg 0 -seg 11 name port p0 port p1 port p2 port p3 port p4 port p5 port p6 port p7 common segment i/o format cmos compatible input level cmos 3-state output cmos compatible input level cmos 3-state output cmos compatible input level cmos 3-state output cmos compatible input level cmos compatible input level cmos 3-state output lcd common output lcd segment output non-port function lcd segment output lcd segment output key input(key-on wake up) interrupt input lcd segment output f clock output external interrupt input serial i/o function i/o external interrupt input real time port function oputput timer i/o timer i/o timer output a-d trigger input a-d conversion input sub-clock generating circuit i/o diagram no. (1) (2) (3) (4) (5) (2) (6) (7) (8) (9) (2) (10) (11) (12) (13) (12) (14) (15) (16) (17) (18) 14 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3822 group fig. 5 port block diagram (1) (1)ports p0, p1 segment output enable bit v l1 /v ss (note) data bus direction register port latch pull-down control segment output enable bit note : bit 0 of direction register v l2 /v l3 (2)ports p2, p4 2 , p4 3 , p5 0 , p5 1 data bus pull-up control key input (key-on wake up) interrupt input int 0 ?nt 3 interrupt input direction register port latch (3)ports p3 4 ?3 7 v l2 /v l3 v l1 /v ss pull-down control segment output enable bit (4)port p4 0 data bus (5)port p4 1 f f output control bit pull-up control data bus port latch direction register (6)port p4 4 pull-up control reception enable bit serial i/o enable bit serial i/o input data bus direction register port latch 15 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3822 group fig. 6 port block diagram (2) pull-up control direction register data bus port latch (7)port p4 5 serial i/o output p4 5 /t x d p-channel output disable bit serial i/o enable bit transmission enable bit serial i/o mode selection bit serial i/o enable bit serial i/o enable bit (8)port p4 6 serial i/o clock input pull-up control data bus serial i/o clock output serial i/o clock-synchronized selection bit direction register port latch serial i/o ready output (9) port p4 7 serial i/o mode selection bit serial i/o enable bit s rdy output enable bit data bus pull-up control direction register port latch (10)ports p5 2 , p5 3 real time port control bit pull-up control data bus port latch direction register date for real time port timer x operating mode bit (pulse output mode selection) cntr 0 interrupt input timer output pull-up control (11) port p5 4 direction register port latch data bus (12) ports p5 5 , p5 7 cntr 1 interrupt input a-d trigger interrupt input pull-up control data bus port latch direction register 16 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3822 group data bus pull-up control timer output t out output control bit (13) port p5 6 direction register port latch (15) port p7 0 data bus port selection/pull-up control port x c switch bit oscillation circuit port p7 1 port x c switch bit direction register port latch (16) port p7 1 data bus port selection/pull-up control port x c switch bit sub-clock generating circuit input direction register port latch v l3 v l2 v l1 (17) com 0 ?om 3 the gate input signal of each transistor is controlled by the lcd duty ratio and the bias value. v ss (18) seg 0 ?eg 11 the voltage applied to the sources of p-channel and n-channel transistors is the controlled voltage by the bias value. v l2 /v l3 v l1 /v ss analog input pin selection bit (14) port p6 data bus pull-up control direction register port latch a-d conversion input fig. 7 port block diagram (3) 17 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3822 group interrupts interrupts occur by seventeen sources: eight external, eight inter- nal, and one software. interrupt control each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except for the software in- terrupt set by the brk instruction. an interrupt occurs if the corre- sponding interrupt request and enable bits are 1 and the inter- rupt disable flag is 0. interrupt enable bits can be set or cleared by software. interrupt request bits can be cleared by software, but cannot be set by software. the brk instruction cannot be disabled with any flag or bit. the i flag disables all interrupts except the brk instruction interrupt. interrupt operation when an interrupt is received, the contents of the program counter and processor status register are automatically stored into the stack. the interrupt disable flag is set to inhibit other interrupts from interfering.the corresponding interrupt request bit is cleared and the interrupt jump destination address is read from the vector table into the program counter. notes on use when the active edge of an external interrupt (int 0 Cint 3 , cntr 0 , or cntr 1 ) is changed, the corresponding interrupt request bit may also be set. therefore, please take following sequence; (1) disable the external interrupt which is selected. (2) change the active edge selection. (3) clear the interrupt request bit which is selected to 0. (4) enable the external interrupt which is selected. notes 1 : vector addresses contain interrupt jump destination addresses. 2 : reset function in the same way as an interrupt with the highest priority. interrupt request generating conditions at reset at detection of either rising or falling edge of int 0 input at detection of either rising or falling edge of int 1 input at completion of serial i/o data reception at completion of serial i/o transmit shift or when transmission buffer is empty at timer x underflow at timer y underflow at timer 2 underflow at timer 3 underflow at detection of either rising or falling edge of cntr 0 input at detection of either rising or falling edge of cntr 1 input at timer 1 underflow at detection of either rising or falling edge of int 2 input at detection of either rising or falling edge of int 3 input at falling of conjunction of input level for port p2 (at input mode) at falling of adt input at completion of a-d conversion at brk instruction execution remarks non-maskable external interrupt (active edge selectable) external interrupt (active edge selectable) valid when serial i/o1 is selected valid when serial i/o1 is selected external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (valid when an l level is applied) valid when adt interrupt is selected external interrupt (valid at falling) valid when a-d interrupt is selected non-maskable software interrupt interrupt source reset (note 2) int 0 int 1 serial i/o reception serial i/o transmission timer x timer y timer 2 timer 3 cntr 0 cntr 1 timer 1 int 2 int 3 key input (key-on wake up) adt a-d conversion brk instruction low fffc 16 fffa 16 fff8 16 fff6 16 fff4 16 fff2 16 fff0 16 ffee 16 ffec 16 ffea 16 ffe8 16 ffe6 16 ffe4 16 ffe2 16 ffe0 16 ffde 16 ffdc 16 high fffd 16 fffb 16 fff9 16 fff7 16 fff5 16 fff3 16 fff1 16 ffef 16 ffed 16 ffeb 16 ffe9 16 ffe7 16 ffe5 16 ffe3 16 ffe1 16 ffdf 16 ffdd 16 table 1. interrupt vector addresses and priority priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 vector addresses (note 1) 18 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3822 group b7 b0 interrupt edge selection register int 0 interrupt edge selection bit int 1 interrupt edge selection bit int 2 interrupt edge selection bit int 3 interrupt edge selection bit not used (return ??when read) (intedge : address 003a 16 ) interrupt request register 1 int 0 interrupt request bit int 1 interrupt request bit serial i/o receive interrupt request bit serial i/o transmit interrupt request bit timer x interrupt request bit timer y interrupt request bit timer 2 interrupt request bit timer 3 interrupt request bit interrupt control register 1 int 0 interrupt enable bit int 1 interrupt enable bit serial i/o receive interrupt enable bit serial i/o transmit interrupt enable bit timer x interrupt enable bit timer y interrupt enable bit timer 2 interrupt enable bit timer 3 interrupt enable bit 0 : no interrupt request issued 1 : interrupt request issued (ireq1 : address 003c 16 ) (icon1 : address 003e 16 ) interrupt request register 2 cntr 0 interrupt request bit cntr 1 interrupt request bit timer 1 interrupt request bit int 2 interrupt request bit int 3 interrupt request bit key input interrupt request bit adt/ad conversion interrupt request bit not used (returns ??when read) (ireq2 : address 003d 16 ) interrupt control register 2 cntr 0 interrupt enable bit cntr 1 interrupt enable bit timer 1 interrupt enable bit int 2 interrupt enable bit int 3 interrupt enable bit key input interrupt enable bit adt/ad conversion interrupt enable bit not used (returns ??when read) (do not write ??to this bit) 0 : interrupts disabled 1 : interrupts enabled (icon2 : address 003f 16 ) 0 : falling edge active 1 : rising edge active b7 b0 b7 b0 b7 b0 b7 b0 0 fig. 8 interrupt control fig. 9 structure of interrupt-related registers interrupt request bit interrupt enable bit interrupt disable flag (i) brk instruction reset interrupt request 19 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3822 group key input interrupt (key-on wake up) a key input interrupt request is generated by applying l level to any pin of port p2 that have been set to input mode. in other words, it is generated when and of input level goes from 1 to 0. an example of using a key input interrupt is shown in figure 10, where an interrupt request is generated by pressing one of the keys consisted as an active-low key matrix which inputs to ports p2 0 Cp2 3 . fig. 10 connection example when using key input interrupt and port p2 block diagram ?? ???? ?? ???? ?? ???? ?? ???? ?? ???? ?? ???? ?? ???? ?? ???? port p2 0 latch port p2 0 direction register = "0" port p2 1 latch port p2 1 direction register = "0" port p2 2 latch port p2 2 direction register = "0" port p2 3 latch port p2 3 direction register = "0" port p2 4 latch port p2 4 direction register = "1" port p2 5 latch port p2 5 direction register = "1" port p2 6 latch port p2 6 direction register = "1" port p2 7 latch port p2 7 direction register = "1" p2 0 input p2 1 input p2 2 input p2 3 input p2 4 output p2 5 output p2 6 output p2 7 output pull register a bit 2 = "1" port p2 input reading circuit port pxx "l" level output ?? ?? p-channel transistor for pull-up ???? cmos output buffer key input interrupt request ]] ] ]] ]] ] ] ]] ] ]] ] ]] ] ]] ] ]] ] ]] ] 20 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3822 group timers the 3822 group has five timers: timer x, timer y, timer 1, timer 2, and timer 3. timer x and timer y are 16-bit timers, and timer 1, timer 2, and timer 3 are 8-bit timers. all timers are down count timers. when the timer reaches 00 16 , an underflow occurs at the next count pulse and the correspond- ing timer latch is reloaded into the timer and the count is contin- ued. when a timer underflows, the interrupt request bit corre- sponding to that timer is set to 1. read and write operation on 16-bit timer must be performed for both high and low-order bytes. when reading a 16-bit timer, read the high-order byte first. when writing to a 16-bit timer, write the low-order byte first. the 16-bit timer cannot perform the correct op- eration when reading during the write operation, or when writing during the read operation. fig. 11 timer block diagram cntr 0 active edge switch bit timer 1 count source selection bit real time port control bit ?? ? p5 5 /cntr 1 ? f(x in )/16 (f(x cin )/16 in low-speed mode ] ) cntr 1 active edge switch bit ?0 timer y stop control bit falling edge detection period measurement mode timer y interrupt request pulse width hl continuously measurement mode rising edge detection ?0??1??1 timer y operating mode bit timer x interrupt request timer x mode register write signal p5 4 /cntr 0 q q t s p5 4 direction register pulse output mode p5 4 latch timer x stop control bit ? ? timer x write control bit q d latch q d latch ? ? ? ?0 timer x operat- ing mode bit ?0??1??1 f(x in )/16 (f(x cin )/16 in low-speed mode ] ) pulse width measurement mode cntr 0 active edge switch bit pulse output mode q q t s ? p5 6 direction register p5 6 latch ? t out output active edge switch bit ? timer 2 write control bit ? ? t out output control bit ? p5 6 /t out x cin timer 3 count source selection bit ? ? timer 2 interrupt request timer 3 interrupt request t out output control bit timer 2 count source selection bit timer 1 interrupt request data bus f(x in )/16 (f(x cin )/16 in low-speed mode ] ) f(x in )/16 (f(x cin )/16 in low-speed mode ] ) f(x in )/16(f(x cin )/16 in low-speed mode ] ) ] internal clock f = x cin /2. cntr 0 interrupt request cntr 1 interrupt request timer y operating mode bit ?0??1??0 ?1 p6 0 direction register ? real time port control bit ? p6 0 p6 0 latch p6 1 direction register ? real time port control bit ? p6 1 p6 1 latch p6 0 data for real time port p6 1 data for real time port timer y (low) (8) timer y (high) (8) timer 3 latch (8) timer 3 (8) timer 1 latch (8) timer 1 (8) timer 2 latch (8) timer 2 (8) timer x (low) (8) timer x (high) (8) timer x (low) latch (8) timer x (high) latch (8) timer y (low) latch (8) timer y (high) latch (8) 21 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3822 group fig. 12 structure of timer x mode register timer x timer x is a 16-bit timer that can be selected in one of four modes and can be controlled the timer x write and the real time port by setting the timer x mode register. timer mode the timer counts f(x in )/16 (or f(x cin )/16 in low-speed mode). pulse output mode each time the timer underflows, a signal output from the cntr 0 pin is inverted. except for this, the operation in pulse output mode is the same as in timer mode. when using a timer in this mode, set the corresponding port p5 4 direction register to output mode. event counter mode the timer counts signals input through the cntr 0 pin. except for this, the operation in event counter mode is the same as in timer mode. when using a timer in this mode, set the corre- sponding port p5 4 direction register to input mode. pulse width measurement mode the count source is f(x in )/16 (or f(x cin )/16 in low-speed mode). if cntr 0 active edge switch bit is 0, the timer counts while the in- put signal of cntr 0 pin is at h. if it is 1, the timer counts while the input signal of cntr 0 pin is at l. when using a timer in this mode, set the corresponding port p5 4 direction register to input mode. timer x write control if the timer x write control bit is 0, when the value is written in the address of timer x, the value is loaded in the timer x and the latch at the same time. if the timer x write control bit is 1, when the value is written in the address of timer x, the value is loaded only in the latch. the value in the latch is loaded in timer x after timer x underflows. if the value is written in latch only, unexpected value may be set in the high-order counter when the writing in high-order latch and the underflow of timer x are performed at the same timing. note on cntr 0 interrupt active edge selec- tion cntr 0 interrupt active edge depends on the cntr 0 active edge switch bit. real time port control while the real time port function is valid, data for the real time port are output from ports p5 2 and p5 3 each time the timer x underflows. (however, after rewriting a data for real time port, if the real time port control bit is changed from 0 to 1, data are output without the timer x.) if the data for the real time port is changed while the real time port function is valid, the changed data are out- put at the next underflow of timer x. before using this function, set the corresponding port direction registers to output mode. timer x mode register (txm : address 0027 16 ) timer x write control bit 0 : write value in latch and counter 1 : write value in latch only real time port control bit 0 : real time port function invalid 1 : real time port function valid p5 2 data for real time port p5 3 data for real time port timer x operating mode bits b5 b4 0 0 : timer mode 0 1 : pulse output mode 1 0 : event counter mode 1 1 : pulse width measurement mode cntr 0 active edge switch bit 0 : count at rising edge in event counter mode start from ??output in pulse output mode measure ??pulse width in pulse width measurement mode falling edge active for cntr 0 interrupt 1 : count at falling edge in event counter mode start from ??output in pulse output mode measure ??pulse width in pulse width measurement mode rising edge active for cntr 0 interrupt timer x stop control bit 0 : count start 1 : count stop b7 b0 22 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3822 group timer y timer y is a 16-bit timer that can be selected in one of four modes. timer mode the timer counts f(x in )/16 (or f(x cin )/16 in low-speed mode). period measurement mode cntr 1 interrupt request is generated at rising/falling edge of cntr 1 pin input signal. simultaneously, the value in timer y latch is reloaded in timer y and timer y continues counting down/except for the above-mentioned, the operation in period measurement mode is the same as in timer mode. the timer value just before the reloading at rising/falling of cntr 1 pin input signal is retained until the timer y is read once after the reload. the rising/falling timing of cntr 1 pin input signal is found by cntr 1 interrupt. when using a timer in this mode, set the corre- sponding port p5 5 direction register to input mode. event counter mode the timer counts signals input through the cntr 1 pin. except for this, the operation in event counter mode is the same as in timer mode. when using a timer in this mode, set the corre- sponding port p5 5 direction register to input mode. pulse width hl continuously measurement mode cntr 1 interrupt request is generated at both rising and falling edges of cntr 1 pin input signal. except for this, the operation in pulse width hl continuously measurement mode is the same as in period measurement mode. when using a timer in this mode, set the corresponding port p5 5 direction register to input mode. note on cntr 1 interrupt active edge selec- tion cntr 1 interrupt active edge depends on the cntr 1 active edge switch bit. however, in pulse width hl continuously measurement mode, cntr 1 interrupt request is generated at both rising and falling edges of cntr 1 pin input signal regardless of the setting of cntr 1 active edge switch bit. fig. 13 structure of timer y mode register timer y mode register (tym : address 0028 16 ) b7 b0 not used (return ??when read) timer y operating mode bits b5 b4 0 0 : timer mode 0 1 : period measurement mode 1 0 : event counter mode 1 1 : pulse width hl continuously measurement mode cntr 1 active edge switch bit 0 : count at rising edge in event counter mode measure the falling edge to falling edge period in period measurement mode falling edge active for cntr 1 interrupt 1 : count at falling edge in event counter mode measure the rising edge period in period measurement mode rising edge active for cntr 1 interrupt timer y stop control bit 0 : count start 1 : count stop 23 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3822 group t out output active edge switch bit 0 : start at h output 1 : start at l output t out output control bit 0 : t out output disabled 1 : t out output enabled timer 2 write control bit 0 : write data in latch and counter 1 : write data in latch only timer 2 count source selection bit 0 : timer 1 output 1 : f(x in )/16 (or f(x cin )/16 in low-speed mode) timer 3 count source selection bit 0 : timer 1 output 1 : f(x in )/16 (or f(x cin )/16 in low-speed mode) timer 1 count source selection bit 0 : f(x in )/16 (or f(x cin )/16 in low-speed mode) 1 : f(x cin ) not used (return 0 when read) timer 123 mode register (t123m : address 0029 16 ) note : internal clock f is f(x cin )/2 in the low-speed mode. b7 b0 timer 1, timer 2, timer 3 timer 1, timer 2, and timer 3 are 8-bit timers. the count source for each timer can be selected by timer 123 mode register. the timer latch value is not affected by a change of the count source. how- ever, because changing the count source may cause an inadvert- ent count down of the timer. therefore, rewrite the value of timer whenever the count source is changed. timer 2 write control if the timer 2 write control bit is 0, when the value is written in the address of timer 2, the value is loaded in the timer 2 and the latch at the same time. if the timer 2 write control bit is 1, when the value is written in the address of timer 2, the value is loaded only in the latch. the value in the latch is loaded in timer 2 after timer 2 underflows. timer 2 output control when the timer 2 (t out ) is output enabled, an inversion signal from pin t out is output each time timer 2 underflows. in this case, set the port p5 6 shared with the port t out to the out- put mode. note on timer 1 to timer 3 when the count source of timer 1 to 3 is changed, the timer count- ing value may be changed large because a thin pulse is generated in count input of timer . if timer 1 output is selected as the count source of timer 2 or timer 3, when timer 1 is written, the counting value of timer 2 or timer 3 may be changed large because a thin pulse is generated in timer 1 output. therefore, set the value of timer in the order of timer 1, timer 2 and timer 3 after the count source selection of timer 1 to 3. fig. 14 structure of timer 123 mode register 24 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3822 group serial i/o serial i/o can be used as either clock synchronous or asynchro- nous (uart) serial i/o. a dedicated timer (baud rate generator) is also provided for baud rate generation. clock synchronous serial i/o mode clock synchronous serial i/o mode can be selected by setting the mode selection bit of the serial i/o control register to 1. for clock synchronous serial i/o, the transmitter and the receiver must use the same clock. if an internal clock is used, transfer is started by a write signal to the tb/rb (address 0018 16 ). fig. 15 block diagram of clock synchronous serial i/o fig. 16 operation of clock synchronous serial i/o function p4 6 /s clk1 p4 7 /s rdy1 p4 4 /r x d p4 5 /t x d f(x in ) 1/4 1/4 f/f serial i/o status register serial i/o control register receive buffer address 0018 16 receive shift register receive buffer full flag (rbf) receive interrupt request (ri) clock control circuit shift clock serial i/o synchronization clock selection bit frequency division ratio 1/(n+1) baud rate generator address 001c 16 brg count source selection bit clock control circuit falling-edge detector data bus address 0018 16 shift clock transmit shift register shift completion flag (tsc) transmit buffer empty flag (tbe) serial i/o transmit interrupt request (ti) transmit interrupt source selection bit address 0019 16 data bus address 001a 16 transmit buffer register (tb) transmit shift register d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 rbf = 1 tsc = 1 tbe = 0 tbe = 1 tsc = 0 transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) serial output t x d serial input r x d write signal to receive/transmit buffer register (address 0018 16 ) overrun error (oe) detection notes 1 : the transmit interrupt (ti) can be selected to occur either when the transmit buffer register has emptied (tbe=1) or after the transmit shift operation has ended (tsc=1), by setting the transmit interrupt source selection bit (tic) of the serial i/o control register. 2 : if data is written to the transmit buffer register when tsc=0, the transmit clock is generated continuously and serial data is output continuously from the t x d pin. 3 : the receive interrupt (ri) is set when the receive buffer full flag (rbf) becomes ??. receive enable signal s rdy1 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 25 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3822 group asynchronous serial i/o1 (uart) mode clock asynchronous serial i/o1 mode (uart) can be selected by clearing the serial i/o mode selection bit of the serial i/o control register to 0. eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. the transmit and receive shift registers each have a buffer regis- ter, but the two buffers have the same address in memory. since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. the transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. fig. 17 block diagram of uart serial i/o fig. 18 operation of uart serial i/o function f(x in ) 1/4 oe pe fe 1/16 1/16 data bus receive buffer register(rb) address 0018 16 receive shift register receive buffer full flag (rbf) serial i/o receive interrupt request (ri) baud rate generator frequency division ratio 1/(n+1) address 001c 16 st/sp/pa generator transmit buffer register data bus transmit shift register address 0018 16 transmit shift register shift completion flag (tsc) transmit buffer empty flag (tbe) transmit interrupt request (ti) address 0019 16 st detector sp detector uart control register address 001b 16 character length selection bit address 001a 16 brg count source selection bit transmit interrupt source selection bit serial i/o synchronization clock selection bit clock control circuit character length selection bit 7 bits 8 bits serial i/o control register p4 6 /s clk1 serial i/o status register p4 4 /r x d p4 5 /t x d tsc=0 tbe=1 rbf=0 tbe=0 tbe=0 rbf=1 rbf=1 st d 0 d 1 sp d 0 d 1 st sp tbe=1 tsc=1 ] st d 0 d 1 sp d 0 d 1 st sp transmit buffer register write signal ] generated at 2nd bit in 2-stop-bit mode 1 start bit 7 or 8 data bits 1 or 0 parity bit 1 or 2 stop bit (s) 1 : error flag detection occurs at the same time that the rbf flag becomes ??(at 1st stop bit, during reception). 2 : the transmit interrupt (ti) can be selected to occur when either the tbe or tsc flag becomes ?? depending on the setting of the transmit interrupt source selection bit (tic) of the serial i/o control register. 3 : the receive interrupt (ri) is set when the rbf flag becomes ?? 4 : after data is written to the transmit buffer register when tsc=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to tsc=0. notes serial output t x d serial input r x d receive buffer register read signal transmit or receive clock 26 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3822 group serial i/o control register (sio1con) 001a 16 the serial i/o control register contains eight control bits for the se- rial i/o function. uart control register (uartcon) 001b 16 the uart control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial i/o is selected and set the data format of an data transfer. one bit in this register (bit 4) is always valid and sets the output structure of the p4 5 /t x d pin. serial i/o status register (sio1sts) 0019 16 the read-only serial i/o status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial i/o function and various errors. three of the flags (bits 4 to 6) are valid only in uart mode. the receive buffer full flag (bit 1) is cleared to 0 when the receive buffer is read. if there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer reg- ister, and the receive buffer full flag is set. a write to the serial i/o status register clears all the error flags oe, pe, fe, and se (bit 3 to bit 6, respectively). writing 0 to the serial i/o enable bit sioe (bit 7 of the serial i/o control register) also clears all the status flags, including the error flags. all bits of the serial i/o status register are initialized to 0 at reset, but if the transmit enable bit (bit 4) of the serial i/o control register has been set to 1, the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become 1. transmit buffer/receive buffer register (tb/ rb) 0018 16 the transmit buffer register and the receive buffer are located at the same address. the transmit buffer register is write-only and the receive buffer register is read-only. if a character bit length is 7 bits, the msb of data stored in the receive buffer register is 0. baud rate generator (brg) 001c 16 the baud rate generator determines the baud rate for serial trans- fer. the baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate genera- tor. 27 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3822 group brg count source selection bit (css) 0: f(x in ) 1: f(x in )/4 serial i/o1 synchronization clock selection bit (scs) 0: brg output divided by 4 when clock synchronized serial i/o is selected. brg output divided by 16 when uart is selected. 1: external clock input when clock synchronized serial i/o is selected. external clock input divided by 16 when uart is selected. s rdy1 output enable bit (srdy) 0: p4 7 pin operates as ordinary i/o pin 1: p4 7 pin operates as s rdy1 output pin transmit interrupt source selection bit (tic) 0: interrupt when transmit buffer has emptied 1: interrupt when transmit shift operation is completed transmit enable bit (te) 0: transmit disabled 1: transmit enabled receive enable bit (re) 0: receive disabled 1: receive enabled serial i/o mode selection bit (siom) 0: asynchronous serial i/o (uart) 1: clock synchronous serial i/o serial i/o enable bit (sioe) 0: serial i/o disabled (pins p4 4 ?4 7 operate as ordinary i/o pins) 1: serial i/o enabled (pins p4 4 ?4 7 operate as serial i/o pins) serial i/o control register (sio1con : address 001a 16 ) b7 b0 transmit buffer empty flag (tbe) 0: buffer full 1: buffer empty receive buffer full flag (rbf) 0: buffer empty 1: buffer full transmit shift register shift completion flag (tsc) 0: transmit shift in progress 1: transmit shift completed overrun error flag (oe) 0: no error 1: overrun error parity error flag (pe) 0: no error 1: parity error framing error flag (fe) 0: no error 1: framing error summing error flag (se) 0: (oe) u (pe) u (fe) =0 1: (oe) u (pe) u (fe) =1 not used (returns ??when read) serial i/o status register (siosts : address 0019 16 ) b7 b0 character length selection bit (chas) 0: 8 bits 1: 7 bits parity enable bit (pare) 0: parity checking disabled 1: parity checking enabled parity selection bit (pars) 0: even parity 1: odd parity stop bit length selection bit (stps) 0: 1 stop bit 1: 2 stop bits p4 5 /t x d p-channel output disable bit (poff) 0: cmos output (in output mode) 1: n-channel open-drain output (in output mode) not used (return ??when read) uart control register (uartcon : address 001b 16 ) b7 b0 fig. 19 structure of serial i/o control registers 28 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3822 group a-d converter the functional blocks of the a-d converter are described below. a-d conversion register (ad) 0035 16 the a-d conversion register is a read-only register that contains the result of an a-d conversion. when reading this register during an a-d conversion, the previous conversion result is read. a-d control register (adcon) 0034 16 the a-d control register controls the a-d conversion process. bits 0 to 2 of this register select specific analog input pins. bit 3 signals the completion of an a-d conversion. the value of this bit remains at 0 during an a-d conversion, then changes to 1 when the a-d conversion is completed. writing 0 to this bit starts the a-d conversion. bit 4 controls the transistor which breaks the through current of the resistor ladder. when bit 5, which is the ad external trigger valid bit, is set to 1, this bit enables a-d conversion even by a falling edge of an adt input. set ports which share with adt pins to input when using an a-d external trigger. comparison voltage generator the comparison voltage generator divides the voltage between av ss and v ref by 256, and outputs the divided voltages. channel selector the channel selector selects one of the input ports p6 7 /an 7 to p6 0 /an 0 . comparator and control circuit the comparator and control circuit compares an analog input volt- age with the comparison voltage and stores the result in the a-d conversion register. when an a-d conversion is completed, the control circuit sets the ad conversion completion bit and the ad interrupt request bit to 1. note that the comparator is constructed linked to a capacitor, so set f(x in ) to at least 500 khz during a-d conversion. fig. 20 structure of a-d control register fig. 21 a-d converter block diagram a-d control register (adcon : address 0034 16 ) ad conversion completion bit 0 : conversion in progress 1 : conversion completed analog input pin selection bits 0 0 0 : p6 0 /an 0 0 0 1 : p6 1 /an 1 0 1 0 : p6 2 /an 2 0 1 1 : p6 3 /an 3 1 0 0 : p6 4 /an 4 1 0 1 : p6 5 /an 5 1 1 0 : p6 6 /an 6 1 1 1 : p6 7 /an 7 v ref input switch bit 0 : off 1 : on ad external trigger valid bit 0 : a-d external trigger invalid 1 : a-d external trigger valid b7 b0 interrupt source selection bit 0 : interrupt request at a-d conversion completed 1 : interrupt request at adt input falling not used (returns ??when read) comparator a-d control circuit adt/a-d interrupt request av ss v ref p6 0 /an 0 data bus a-d control register b7 b0 a-d conversion register resistor ladder channel selector p6 7 /an 7 p6 6 /an 6 p6 5 /an 5 p6 4 /an 4 p6 3 /an 3 p6 2 /an 2 p6 1 /an 1 p5 7 /adt 8 3 29 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3822 group lcd drive control circuit the 3822 group has the built-in liquid crystal display (lcd) drive control circuit consisting of the following. ? lcd display ram ? segment output enable register ? lcd mode register ? selector ? timing controller ? common driver ? segment driver ? bias control circuit a maximum of 32 segment output pins and 4 common output pins can be used. up to 128 pixels can be controlled for lcd display. when the lcd enable bit is set to 1 after data is set in the lcd mode register, fig. 22 structure of segment output enable register and lcd mode register the segment output enable register and the lcd display ram, the lcd drive control circuit starts reading the display data automati- cally, performs the bias control and the duty ratio control, and dis- plays the data on the lcd panel. table 2. maximum number of display pixels at each duty ratio duty ratio maximum number of display pixel 64 dots or 8 segment lcd 8 digits 96 dots or 8 segment lcd 12 digits 128 dots or 8 segment lcd 16 digits 2 3 4 segment output enable bit 0 0 : input ports p3 4 ?3 7 1 : segment output seg 12 ?eg 15 segment output enable bit 1 0 : i/o ports p0 0 , p0 1 1 : segment output seg 16 ,seg 17 segment output enable bit 2 0 : i/o ports p0 2 ?0 7 1 : segment output seg 18 ?eg 23 segment output enable bit 3 0 : i/o ports p1 0 ,p1 1 1 : segment output seg 24 ,seg 25 segment output enable bit 4 0 : i/o port p1 2 1 : segment output seg 26 segment output enable bit 5 0 : i/o ports p1 3 ?1 7 1 : segment output seg 27 ?eg 31 not used (return ??when read) (do not write ??to this bit) segment output enable register (seg : address 0038 16 ) b7 b0 lcd mode register (lm : address 0039 16 ) duty ratio selection bits 0 0 : not available 0 1 : 2 (use com 0 ,com 1 ) 1 0 : 3 (use com 0 ?om 2 ) 1 1 : 4 (use com 0 ?om 3 ) bias control bit 0 : 1/3 bias 1 : 1/2 bias lcd enable bit 0 : lcd off 1 : lcd on not used (returns ??when read) (do not write ??to this bit) lcd circuit divider division ratio selection bits 0 0 : clock input 0 1 : 2 division of clock input 1 0 : 4 division of clock input 1 1 : 8 division of clock input lcdck count source selection bit (note) 0 : f(x cin )/32 1 : f(x in )/8192 note : lcdck is a clock for a lcd timing controller. b7 b0 30 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3822 group fig. 23 block diagram of lcd controller/driver data bus timing controller lcd divider f(x cin )/32 f(x in )/8192 common driver bias control com 0 com 1 com 2 com 3 v ss v l1 v l2 v l3 seg 3 seg 2 seg 1 seg 0 address 0040 16 address 0041 16 ? ? lcdck lcdck count source selection bit lcd circuit divider division ratio selection bits bias control bit lcd enable bit duty ratio selection bits 2 2 selector selector selector selector selector selector lcd display ram address 004f 16 p1 6 /seg 30 p3 4 /seg 12 p1 7 /seg 31 segment driver segment driver segment driver segment driver segment driver segment driver common driver common driver common driver 31 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3822 group bias control and applied voltage to lcd power input pins to the lcd power input pins (v l1 Cv l3 ), apply the voltage shown in table 3 according to the bias value. select a bias value by the bias control bit (bit 2 of the lcd mode register). common pin and duty ratio control the common pins (com 0 Ccom 3 ) to be used are determined by duty ratio. select duty ratio by the duty ratio selection bits (bits 0 and 1 of the lcd mode register). fig. 24 example of circuit at each bias table 3. bias control and applied voltage to v l1 Cv l3 bias value 1/3 bias 1/2 bias voltage value v l3 =v lcd v l2 =2/3 v lcd v l1 =1/3 v lcd v l3 =v lcd v l2 =v l1 =1/2 v lcd note 1 :v lcd is the maximum value of supplied voltage for the lcd panel. table 4. duty ratio control and common pins used duty ratio 2 3 4 common pins used notes 1 : com 2 and com 3 are open 2 : com 3 is open bit 1 0 1 1 bit 0 1 0 1 com 0 , com 1 (note 1) com 0 Ccom 2 (note 2) com 0 Ccom 3 duty ratio selection bit v l3 v l2 v l1 r4 r5 r4 = r5 contrast control 1/2 bias v l3 v l2 v l1 contrast control r1 r2 r3 r1 = r2 = r3 1/3 bias 32 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3822 group lcd display ram address 0040 16 to 004f 16 is the designated ram for the lcd dis- play. when 1 are written to these addresses, the corresponding segments of the lcd display panel are turned on. lcd drive timing the lcdck timing frequency (lcd drive timing) is generated in- ternally and the frame frequency can be determined with the fol- lowing equation; (frequency of count source for lcdck) (divider division ratio for lcd) f(lcdck)= f(lcdck) duty ratio frame frequency= fig. 25 lcd display ram map bit address 0046 16 0047 16 0048 16 0049 16 004a 16 004b 16 004c 16 004d 16 004e 16 004f 16 seg 13 seg 15 seg 17 seg 19 seg 21 seg 23 seg 25 seg 27 seg 29 seg 31 0040 16 0041 16 0042 16 0043 16 0044 16 0045 16 seg 1 seg 3 seg 5 seg 7 seg 9 seg 11 76543210 com 3 com 0 com 2 com 1 com 0 com 3 com 2 com 1 seg 12 seg 14 seg 16 seg 18 seg 20 seg 22 seg 24 seg 26 seg 28 seg 30 seg 0 seg 2 seg 4 seg 6 seg 8 seg 10 33 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3822 group fig. 26 lcd drive waveform (1/2 bias) internal logic lcdck timing 1/4 duty voltage level v l3 v l2 =v l1 v ss v l3 v ss com 0 com 1 com 2 com 3 seg 0 off on off on com 3 com 2 com 1 com 0 com 3 com 2 com 1 com 0 1/3 duty v l3 v l2 =v l1 v ss v l3 v ss off on on off on off 1/2 duty com 0 com 1 com 2 seg 0 com 0 com 1 seg 0 v l3 v l2 =v l1 v ss v l3 v ss off on off on off on off on com 0 com 2 com 1 com 0 com 2 com 1 com 0 com 2 com 1 com 0 com 1 com 0 com 1 com 0 com 1 com 0 34 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3822 group fig. 27 lcd drive waveform (1/3 bias) internal logic lcdck timing 1/4 duty voltage level v l3 v ss com 0 com 1 com 2 com 3 seg 0 off on off on com 3 com 2 com 1 com 0 com 3 com 2 com 1 com 0 1/3 duty off on on off on off 1/2 duty com 0 com 1 com 2 seg 0 com 0 com 1 seg 0 off on off on off on off on v l3 v l2 v ss v l1 v l3 v l2 v ss v l1 v l3 v ss v l3 v l2 v ss v l1 v l3 v ss com 0 com 2 com 1 com 0 com 2 com 1 com 0 com 2 com 1 com 0 com 1 com 0 com 1 com 0 com 1 com 0 35 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3822 group f clock output function the internal system clock f can be output from port p4 1 by setting the f output control register. set bit 1 of the port p4 direction reg- ister to when outputting f clock. fig. 28 structure of f output control register f output control bit 0 : port function 1 : f clock output f output control register (ckout : address 002a 16 ) b7 b0 not used (return 0 when read) 36 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3822 group reset circuit to reset the microcomputer, reset pin should be held at an l level for 2 m s or more. then the reset pin is returned to an h level (the power source voltage should be between 2.5 v and 5.5 v, and the oscillation should be stable), reset is released. in or- der to give the x in clock time to stabilize, internal operation does not begin until after 8200 x in clock cycles (timer 1 and timer 2 are connected together and 512 cycles of f(x in )/16) are complete. af- ter the reset is completed, the program starts from the address contained in address fffd 16 (high-order byte) and address fffc 16 (low-order byte). make sure that the reset input voltage is less than 0.5 v for v cc of 2.5 v (extended operating temperature version: the reset input voltage is less than 0.6v for v cc of 3.0v). fig. 30 internal state of microcomputer after reset fig. 29 example of reset circuit (note) 0.2v cc 0v 0v note. reset release voltage : v cc = 2.5v (extended operating temperature version : 3.0v) power on v cc reset v cc reset power source voltage detection circuit reset input voltage power source voltage register contents (0001 16 ) ?? timer y (low) port p0 direction register port p1 direction register port p2 direction register pull register b timer y (high) serial i/o control register uart control register timer x (high) (10) (11) (12) (13) (14) (15) (16) (17) (18) (19) (20) (21) (22) (23) (24) (0003 16 ) ?? (0005 16 ) ?? (0017 16 ) ?? (001a 16 ) ?? (001b 16 ) ?? (0020 16 ) ?? (0021 16 ) ?? (0022 16 ) ?? (0023 16 ) ?? (0024 16 ) ?? (0025 16 ) ?? (0026 16 ) ?? (0027 16 ) ?? (0028 16 ) ?? (0029 16 ) ?? (002a 16 ) ?? address timer x (low) timer 1 timer 2 timer 3 timer x mode register timer y mode register timer 123 mode register f output control register 00 16 (000f 16 ) ?? 111000 0 0 serial i/o status register (0019 16 ) ?? 100000 0 0 port p4 direction register port p5 direction register port p6 direction register (0009 16 ) ?? (000b 16 ) ?? (000d 16 ) ?? (25) (26) (27) (0034 16 ) ?? (0038 16 ) ?? (0039 16 ) ?? a-d control register segment output enable register lcd mode register pull register a (0016 16 ) ?? 000010 1 1 note 5 : undefined the contents of all other registers and ram are undefined after reset, so they must be initialized by software. (28) (29) (30) (31) (32) (33) (34) (003a 16 ) ??? (003b 16 ) ?? (003c 16 ) ?? (003d 16 ) ?? (003e 16 ) ?? interrupt edge selection register cpu mode register interrupt request register 1 interrupt request register 2 interrupt control register 1 interrupt control register 2 processor status register program counter 1 0 0 1 00 0 contents of address fffc 16 5 (ps) (pc h ) (pc l ) contents of address fffd 16 (003f 16 ) ?? 000010 0 0 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 ( 1 ) ( 2 ) ( 3 ) ( 4 ) ( 5 ) ( 6 ) ( 7 ) ( 8 ) ( 9 ) 0 1 5 5 55 55 ff 16 ff 16 ff 16 ff 16 ff 16 01 16 ff 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 port p7 direction register 37 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3822 group fig. 31 reset sequence ad l fffc fffd ad h , ad l ?? ? ? x in : about 8200 clock cycles notes 1 : f(x in ) and f( f) are in the relationship : f(x in ) = 8 f( f ) notes 2 : a question mark (?) indicates an undefined status that depe nds on the previous status. reset address from vector table reset internal reset address data sync f x in ad h 38 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3822 group x in x out external oscillation circuit open v cc v ss c cin c cout rf rd x cin x cout x cin x cout x in x out c in c out c cin c cout rf rd clock generating circuit the 3822 group has two built-in oscillation circuits. an oscillation circuit can be formed by connecting a resonator between x in and x out (x cin and x cout ). use the circuit constants in accordance with the resonator manufacturer's recommended values. no exter- nal resistor is needed between x in and x out since a feed-back re- sistor exists on-chip. however, an external feed-back resistor is needed between x cin and x cout . to supply a clock signal externally, input it to the x in pin and make the x out pin open. the sub-clock x cin -x cout oscillation circuit cannot directly input clocks that are externally generated. accord- ingly, be sure to cause an external resonator to oscillate. immediately after poweron, only the x in oscillation circuit starts oscillating, and x cin and x cout pins function as i/o ports. the pull-up resistor of x cin and x cout pins must be made invalid to use the sub-clock. frequency control middle-speed mode the internal clock f is the frequency of x in divided by 8. after reset, this mode is selected. high-speed mode the internal clock f is half the frequency of x in . low-speed mode ? the internal clock f is half the frequency of x cin . ? a low-power consumption operation can be realized by stopping the main clock x in in this mode. to stop the main clock, set bit 5 of the cpu mode register to 1. when the main clock x in is restarted, set enough time for oscil- lation to stabilize by programming. note: if you switch the mode between middle/high-speed and low- speed, stabilize both x in and x cin oscillations. the suffi- cient time is required for the sub-clock to stabilize, espe- cially immediately after poweron and at returning from stop mode. when switching the mode between middle/high- speed and low-speed, set the frequency on condition that f(x in )>3f(x cin ). fig. 32 ceramic resonator circuit fig. 33 external clock input circuit oscillation control stop mode if the stp instruction is executed, the internal clock f stops at an h level, and x in and x cin oscillators stop. timer 1 is set to ff 16 and timer 2 is set to 01 16 . either x in or x cin divided by 16 is input to timer 1 as count source, and the output of timer 1 is connected to timer 2. the bits of the timer 123 mode register except bit 4 are cleared to 0. set the timer 1 and timer 2 interrupt enable bits to disabled (0) before executing the stp instruction. oscillator restarts at reset or when an external interrupt is re- ceived, but the internal clock f is not supplied to the cpu until timer 2 underflows. this allows time for the clock circuit oscillation to stabilize. wait mode if the wit instruction is executed, the internal clock f stops at an h level. the states of x in and x cin are the same as the state be- fore the executing the wit instruction. the internal clock restarts at reset or when an interrupt is received. since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. 39 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3822 group fig. 34 clock generating circuit block diagram wit instruction stp instruction timing f (internal system clock) s r q stp instruction s r q main clock stop bit s r q timer 2 timer 1 1/2 1/4 x in x out x cout x cin interrupt request reset port x c switch bit 1 0 timer 1 count source selection bit timer 2 count source selection bit low-speed mode middle-/high-speed mode internal system clock selection bit (note) middle-speed mode high-speed mode or low-speed mode note : when using the low-speed mode, set the port x c switch bit to 1 . main clock division ratio selection bit 1 0 1 0 1 0 interrupt disable flag i 1/2 40 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3822 group fig. 35 state transitions of internal clock notes 1 : switch the mode by the allows shown between the mode blocks. (do not switch between the mode directly without an allow.) 2 : the all modes can be switched to the stop mode or the wait mode and returned to the source mode when the stop mode or the wait mode is ended. 3 : timer and lcd operate in the wait mode. 4 : when the stop mode is ended, a delay of approximately 1 ms occurs automatically by timer 1 and timer 2 in middle-/high-speed mode. 5 : when the stop mode is ended, a delay of approximately 0.25 s occurs automatically by timer 1 and timer 2 in low-speed mode. 6 : wait until oscillation stabilizes after oscillating the main clock x in before the switching from the low-speed mode to middle-/high- speed mode. 7 : the example assumes that 8 mhz is being applied to the x in pin and 32 khz to the x cin pin. f indicates the internal clock. cm 4 : port xc switch bit 0: i/o port 1: x cin , x cout cm 5 : main clock (x in Cx out ) stop bit 0: oscillating 1: stopped cm 6 : main clock division ratio selection bit 0: f(x in )/2 (high-speed mode) 1: f(x in )/8 (middle-speed mode) cm 7 : internal system clock selection bit 0: x in Cx out selected (middle-/high-speed mode) 1: x cin Cx cout selected (low-speed mode) cpu mode register (cpum : address 003b 16 ) b7 b4 reset cm 6 0 1 cm 4 0 1 cm 7 =0(8 mhz selected) cm 6 =1(middle-speed) cm 5 =0(8 mhz oscillating) cm 4 =0(32 khz stopped) middle-speed mode (f( f ) =1 mhz) cm 7 =0(8 mhz selected) cm 6 =1(middle-speed) cm 5 =0(8 mhz oscillating) cm 4 =1(32 khz oscillating) middle-speed mode (f( f ) =1 mhz) cm 7 =0(8 mhz selected) cm 6 =0(high-speed) cm 5 =0(8 mhz oscillating) cm 4 =0(32 khz stopped) high-speed mode (f( f ) =4 mhz) cm 7 =0(8 mhz selected) cm 6 =0(high-speed) cm 5 =0(8 mhz oscillating) cm 4 =1(32 khz oscillating) high-speed mode (f( f ) =4 mhz) cm 7 =1(32 khz selected) cm 6 =1(middle-speed) cm 5 =0(8 mhz oscillating) cm 4 =1(32 khz oscillating) low-speed mode (f( f ) =16 khz) cm 7 =1(32 khz selected) cm 6 =0(high-speed) cm 5 =0(8 mhz oscillating) cm 4 =1(32 khz oscillating) low-speed mode (f( f ) =16 khz) cm 7 =1(32 khz selected) cm 6 =1(middle-speed) cm 5 =1(8 mhz stopped) cm 4 =1(32 khz oscillating) low-speed mode (f( f ) =16 khz) cm 7 =1(32 khz selected) cm 6 =0(high-speed) cm 5 =1(8 mhz stopped) cm 4 =1(32 khz oscillating) low-speed mode (f( f ) =16 khz) cm 6 0 1 cm 6 0 1 cm 6 0 1 cm 4 0 1 cm 7 0 1 cm 7 0 1 cm 5 0 1 cm 5 0 1 cm 4 cm 6 0 1 0 1 cm 4 cm 6 0 1 1 0 cm 5 cm 6 0 1 0 1 cm 5 cm 6 0 1 1 0 41 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3822 group notes on programming processor status register the contents of the processor status register (ps) after a reset are undefined, except for the interrupt disable flag (i) which is 1. af- ter a reset, initialize flags which affect program execution. in particular, it is essential to initialize the index x mode (t) and the decimal mode (d) flags because of their effect on calculations. interrupt the contents of the interrupt request bits do not change immedi- ately after they have been written. after writing to an interrupt re- quest register, execute at least one instruction before performing a bbc or bbs instruction. decimal calculations to calculate in decimal notation, set the decimal mode flag (d) to 1, then execute an adc or sbc instruction. only the adc and sbc instructions yield proper decimal results. after executing an adc or sbc instruction, execute at least one instruction before executing a sec, clc, or cld instruction. in decimal mode, the values of the negative (n), overflow (v), and zero (z) flags are invalid. the carry flag can be used to indicate whether a carry or borrow has occurred. initialize the carry flag before each calculation. clear the carry flag before an adc and set the flag before an sbc. timers if a value n (between 0 and 255) is written to a timer latch, the fre- quency division ratio is 1/(n + 1). multiplication and division instructions the index mode (t) and the decimal mode (d) flags do not affect the mul and div instruction. the execution of these instructions does not change the contents of the processor status register. ports the contents of the port direction registers cannot be read. the following cannot be used: ? the data transfer instruction (lda, etc.) ? the operation instruction when the index x mode flag (t) is 1 ? the addressing mode which uses the value of a direction regis- ter as an index ? the bit-test instruction (bbc or bbs, etc.) to a direction register ? the read-modify-write instruction (ror, clb, or seb, etc.) to a direction register use instructions such as ldm and sta, etc., to set the port direc- tion registers. serial i/o in clock synchronous serial i/o, if the receive side is using an ex- ternal clock and it is to output the s rdy signal, set the transmit en- able bit, the receive enable bit, and the s rdy output enable bit to 1. serial i/o continues to output the final bit from the t x d pin after transmission is completed. a-d converter the comparator uses internal capacitors whose charge will be lost if the clock frequency is too low. make sure that f(x in ) is at least 500 khz during an a-d conversion. do not execute the stp or wit instruction during an a-d conver- sion. instruction execution time the instruction execution time is obtained by multiplying the fre- quency of the internal clock f by the number of cycles needed to execute an instruction. the number of cycles required to execute an instruction is shown in the list of machine instructions. the frequency of the internal clock f is half of the x in frequency. 42 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3822 group programming with prom programmer screening (caution) (150 c for 40 hours) verification with prom programmer functional check in target device the screening temperature is far higher than the storage temperature. never expose to 150 c exceeding 100 hours. caution : data required for mask orders the following are necessary when ordering a mask rom produc- tion: (1) mask rom order confirmation form (2) mark specification form (3) data to be written to rom, in eprom form (three identical copies) rom programming method the built-in prom of the blank one time prom version and built- in eprom version can be read or programmed with a general- purpose prom programmer using a special programming adapter. set the address of prom programmer in the user rom area. the prom of the blank one time prom version is not tested or screened in the assembly process and following processes. to en- sure proper operation after programming, the procedure shown in figure 36 is recommended to verify programming. fig. 36 programming and testing of one time prom version package 80p6n-a 80p6s-a 80p6d-a 80d0 name of programming adapter pca4738f-80a pca4738g-80 pca4738h-80 pca4738l-80a single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3822 group 43 high-speed mode f(x in )=8 mhz middle-speed mode f(x in )=8 mhz low-speed mode power source voltage a-d conversion reference input voltage analog power source voltage analog input voltage an 0 Cam 7 h input voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p3 4 Cp3 7 , p4 0 , p4 1 , p4 5 , p4 7 , p5 2 , p5 3 , p5 6 , p6 0 Cp6 7 , p7 0 , p7 1 (cm 4 =0) h input voltage p2 0 Cp2 7 , p4 2 Cp4 4 , p4 6 , p5 0 , p5 1 , p5 4 , p5 5 , p5 7 h input voltage reset h input voltage x in l input voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p3 4 Cp3 7 , p4 0 , p4 1 , p4 5 , p4 7 , p5 2 , p5 3 , p5 6 , p6 0 Cp6 7 , p7 0 , p7 1 (cm 4 =0) l input voltage p2 0 Cp2 7 , p4 2 Cp4 4 , p4 6 , p5 0 , p5 1 , p5 4 , p5 5 , p5 7 l input voltage reset l input voltage x in recommended operating conditions t a = C20 to 85 c t a = C40 to C20 c t a = C20 to 85 c t a = C40 to C20 c absolute maximum ratings power source voltage input voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 4 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 , p7 1 input voltage v l1 input voltage v l2 input voltage v l3 input voltage reset, x in output voltage p0 0 Cp0 7 , p1 0 Cp1 7 output voltage p3 4 Cp3 7 output voltage p2 0 Cp2 7 , p4 1 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 , p7 1 output voltage seg 0 Cseg 11 output voltage x out power dissipation operating temperature storage temperature v cc v i v i v i v i v i v o v o v o v o v o pd topr tstg symbol parameter conditions ratings C0.3 to 7.0 C0.3 to v cc +0.3 C0.3 to v l2 v l1 to v l3 v l2 to v cc +0.3 C0.3 to v cc +0.3 C0.3 to v cc +0.3 C0.3 to v l3 +0.3 C0.3 to v l3 +0.3 C0.3 to v cc +0.3 C0.3 to v l3 +0.3 C0.3 to v cc +0.3 300 C20 to 85 (note 1) C40 to 125 (note 2) v v v v v v v v v v v v mw c c unit all voltages are based on v ss . output transistors are cut off. at output port at segment output at segment output t a = 25 c (v cc = 2.5 to 5.5 v, t a = C20 to 85 c, unless otherwise noted. 5.5 5.5 5.5 5.5 5.5 v cc v cc v cc v cc v cc v cc 0.3 v cc 0.2 v cc 0.2 v cc 0.2 v cc v cc v ss v ref av ss v ia v ih v ih v ih v ih v il v il v il v il symbol parameter limits min. v v v v v v v v v unit 4.0 2.5 3.0 2.5 3.0 2 av ss 0.7 v cc 0.8 v cc 0.8 v cc 0.8 v cc 0 0 0 0 5.0 5.0 5.0 5.0 5.0 0 0 typ. max. notes 1 : extended operating temperature version : C40 to 85 c 2 : extended operating temperature version : C65 to 150 c power source voltage v extended operating temperature version : v cc = 3.0 to 5.5 v, t a = C40 to C20 c and v cc = 2.5 to 5.5v, t a = C20 to 85 c) v v v 44 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3822 group recommended operating conditions (v cc = 2.5 to 5.5 v, t a = C20 to 85 c, unless otherwise noted. extended operating temperature version : v cc = 3.0 to 5.5 v, t a = C40 to C20 c and v cc = 2.5 to 5.5 v, t a = C20 to 85 c) mhz mhz C40 C40 40 40 C20 C20 20 20 C2 C5 5 10 C1.0 C2.5 2.5 5.0 8.0 (4xv cc )C8 8.0 50 h total peak output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 (note 1) h total peak output current p4 1 Cp4 7 ,p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 , p7 1 (note 1) l total peak output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 (note 1) l total peak output current p4 1 Cp4 7 ,p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 , p7 1 (note 1) h total average output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 (note 1) h total average output current p4 1 Cp4 7 ,p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 , p7 1 (note 1) l total average output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 (note 1) l total average output current p4 1 Cp4 7 ,p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 , p7 1 (note 1) h peak output current p0 0 Cp0 7 , p1 0 Cp1 7 (note 2) h peak output current p2 0 Cp2 7 , p4 1 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 , p7 1 (note 2) l peak output current p0 0 Cp0 7 , p1 0 Cp1 7 (note 2) l peak output current p2 0 Cp2 7 , p4 1 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 , p7 1 (note 2) h average output current p0 0 Cp0 7 , p1 0 Cp1 7 (note 3) h average output current p2 0 Cp2 7 , p4 1 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 , p7 1 (note 3) l average output current p0 0 Cp0 7 , p1 0 Cp1 7 (note 3) l average output current p2 0 Cp2 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 , p7 1 (note 3) input frequency for timers x and y (duty cycle 50 %) main clock input oscillation frequency (note 4) sub-clock input oscillation frequency (note 4, 5) notes 1 : the total output current is the sum of all the currents flowing through all the applicable ports. the total average current is an av- erage value measured over 100 ms. the total peak current is the peak value of all the currents. 2 : the peak output current is the peak current flowing in each port. 3 : the average output current is an average value measured over 100 ms. 4 : when the oscillation frequency has a duty cycle of 50%. 5 : when using the microcomputer in low-speed mode, make sure that the sub-clock input oscillation frequency on condition that f(x cin ) < f(x in )/3. s i oh(peak) s i oh(peak) s i ol(peak) s i ol(peak) s i oh(avg) s i oh(avg) s i ol(avg) s i ol(avg) i oh(peak) i oh(peak) i ol(peak) i ol(peak) i oh(avg) i oh(avg) i ol(avg) i ol(avg) f(cntr 0 ) f(cntr 1 ) f(x in ) f(x cin ) symbol parameter limits min. ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma mhz mhz mhz khz unit typ. max. 4.0 v v cc 5.5 v 2.5 v v cc 4.0 v 32.768 high-speed mode (4.0 v v cc 5.5 v) high-speed mode (2.5 v v cc 4.0 v) middle-speed mode 4.0 (2xv cc )C4 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3822 group 45 electrical characteristics (v cc = 4.0 to 5.5 v, t a = C20 to 85 c, unless otherwise noted. extended operating temperature version : v cc = 3.0 to 5.5 v, t a = C40 to C20 c and v cc = 2.5 to 5.5 v, t a = C20 to 85 c) i oh = C2.5 ma i oh = C0.6 ma v cc = 2.5 v i oh = C5 ma i oh = C1.25 ma i oh = C1.25 ma v cc = 2.5 v i ol = 5 ma i ol = 1.25 ma i ol = 1.25 ma v cc = 2.5 v i ol = 10 ma i ol = 2.5 ma i ol = 2.5 ma v cc = 2.5 v reset: v cc =2.5 v to 5.5 v v i = v cc pull-downs off v cc = 5.0 v, v i = v cc pull-downs on v cc = 3.0 v, v i = v cc pull-downs on v i = v cc v i = v cc v i = v cc v i = v ss pull-ups off v cc = 5.0 v, v i = v ss pull-ups on v cc = 3.0 v, v i = v ss pull-ups on v i = v ss v i = v ss t a = C20 to 85 c t a = C40 to C20 c t a = C20 to 85 c t a = C40 to C20 c 2.0 0.5 1.0 2.0 0.5 1.0 5.0 140 170 45 55 5.0 5.0 C5.0 C5.0 C140 C45 C5.0 v cc C2.0 v cc C1.0 v cc C2.0 v cc C0.5 v cc C1.0 30 6.0 C30 C6 v t+ C v tC v t+ C v tC v t+ C v tC i ih i ih i ih i ih i il i il i il i il note 1 : when 1 is set to port x c switch bit (bit 4 of address 003b 16 ) of cpu mode register, the drive ability of port p7 0 is different from the value above mentioned. h output voltage p0 0 Cp0 7 , p1 0 Cp1 7 h output voltage p2 0 Cp2 7 , p4 1 Cp4 7 ,p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 , p7 1 (note 1) l output voltage p0 0 Cp0 7 , p1 0 Cp1 7 l output voltage p2 0 Cp2 7 , p4 1 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 , p7 1 (note 1) hysteresis cntr 0 , cntr 1 , int 0 Cint 3, p2 0 Cp2 7 hysteresis r x d, s clk hysteresis reset h input current p0 0 Cp0 7 , p1 0 Cp1 7 , p3 0 Cp3 7 h input current p2 0 Cp2 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 , p7 1 h input current reset h input current x in l input current p0 0 Cp0 7 , p1 0 Cp1 7 , p3 4 Cp3 7 , p4 0 l input current p2 0 Cp2 7 , p4 1 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 l input current reset l input current x in symbol parameter limits min. v v v v v v v v v v v v v v m a m a m a m a m a m a m a m a m a m a m a m a unit 0.5 0.5 0.5 70 70 25 25 4.0 C70 C25 C4.0 typ. max. test conditions v oh v oh v ol v ol 46 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3822 group electrical characteristics (v cc = 2.5 to 5.5 v, t a = C20 to 85 c, unless otherwise noted. extended operating temperature version : v cc = 3.0 to 5.5 v, t a = C40 to C20 c and v cc = 2.5 to 5.5 v, t a = C20 to 85 c) 13 3.2 36 14.0 22 9.0 1.0 10 ? high-speed mode, v cc = 5 v f(x in ) = 8 mhz f(x cin ) = 32.768 khz output transistors off a-d converter in operating ? high-speed mode, v cc = 5 v f(x in ) = 8 mhz (in wit state) f(x cin ) = 32.768 khz output transistors off a-d converter stopped ? low-speed mode, v cc = 5 v, t a 55 c f(x in ) = stopped f(x cin ) = 32.768 khz output transistors off ? low-speed mode, v cc = 5 v, t a = 25 c f(x in ) = stopped f(x cin ) = 32.768 khz (in wit state) output transistors off ? low-speed mode, v cc = 3 v, t a 55 c f(x in ) = stopped f(x cin ) = 32.768 khz output transistors off ? low-speed mode, v cc = 3 v, t a = 25 c f(x in ) = stopped f(x cin ) = 32.768 khz (in wit state) output transistors off all oscillation stopped (in stp state) output transistors off symbol parameter limits min. unit typ. max. t a = 25 c t a = 85 c test conditions i cc ma ma m a m a m a m a m a power source current 6.4 1.6 25 7.0 15 4.5 0.1 v ram ram hold voltage when clock is stopped 2.0 5.5 v single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3822 group 47 a-d converter characteristics ( v cc = 4.0 to 5.5 v, v ss = 0 v, t a = C20 to 85 c, 4 mhz f(x in ) 8 mhz, middle-/high-speed mode, unless otherwise noted. extended operating temperature version : v cc = 3.0 to 5.5 v, t a = C40 to C20 c and v cc = 2.5 to 5.5 v, t a = C20 to 85 c) symbol parameter limits min. unit typ. max. test conditions C C t conv r ladder v ref i ia resolution absolute accuracy (excluding quantization error) conversion time ladder resistor reference input current analog port input current v cc = v ref = 5 v 12 50 bits lsb m s k w m a m a f(x in ) = 8 mhz v ref = 5 v 12.5 (note) 35 150 8 2 100 200 5.0 note : when an internal trigger is used in middle-speed mode, it is 14 m s. 48 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3822 group t w(reset) t c(x in ) t wh(x in ) t wl(x in ) t c(cntr) t wh(cntr) t wl(cntr) t wh(int) t wl(int) t c(s clk ) t wh(s clk ) t wl(s clk ) t su(r x dCs clk ) t h(s clk Cr x d) 2 125 45 40 500 230 230 230 230 2000 950 950 400 200 timing requirements 1 (v cc = 4.0 to 5.5 v, v ss = 0 v, t a = C20 to 85 c, unless otherwise noted. timing requirements 2 (v cc = 2.5 to 4.0 v, v ss = 0 v, t a = C20 to 85 c, unless otherwise noted. 2 125 45 40 200 80 80 80 80 800 370 370 220 100 note : when f(x in ) = 8 mhz and bit 6 of address 001a 16 is 1 (clock synchronous). divide this value by four when f(x in ) = 8 mhz and bit 6 of address 001a 16 is 0 (uart). reset input l pulse width main clock input cycle time (x in input) main clock input h pulse width main clock input l pulse width cntr 0 , cntr 1 input cycle time cntr 0 , cntr 1 input h pulse width cntr 0 , cntr 1 input l pulse width int 0 to int 3 input h pulse width int 0 to int 3 input l pulse width serial i/o clock input cycle time (note) serial i/o clock input h pulse width (note) serial i/o clock input l pulse width (note) serial i/o input set up time serial i/o input hold time t w(reset) t c(x in ) t wh(x in ) t wl(x in ) t c(cntr) t wh(cntr) t wl(cntr) t wh(int) t wl(int) t c(s clk ) t wh(s clk ) t wl(s clk ) t su(r x dCs clk ) t h(s clk Cr x d) symbol parameter limits min. m s ns ns ns ns ns ns ns ns ns ns ns ns ns unit typ. max. extended operating temperature version : v cc = 3.0 to 5.5 v, t a = C40 to C20 c and v cc = 2.5 to 5.5 v, t a = C20 to 85 c) reset input l pulse width main clock input cycle time (x in input) main clock input h pulse width main clock input l pulse width cntr 0 , cntr 1 input cycle time cntr 0 , cntr 1 input h pulse width cntr 0 , cntr 1 input l pulse width int 0 to int 3 input h pulse width int 0 to int 3 input l pulse width serial i/o clock input cycle time (note) serial i/o clock input h pulse width (note) serial i/o clock input l pulse width (note) serial i/o input set up time serial i/o input hold time symbol parameter limits min. m s ns ns ns ns ns ns ns ns ns ns ns ns ns unit typ. max. note : when f(x in ) = 2 mhz and bit 6 of address 001a 16 is 1 (clock synchronous). divide this value by four when f(x in ) = 2 mhz and bit 6 of address 001a 16 is 0 (uart). extended operating temperature version : v cc = 3.0 to 5.5 v, t a = C40 to C20 c and v cc = 2.5 to 5.5 v, t a = C20 to 85 c) single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3822 group 49 measurement output pin 100 pf cmos output note : when bit 4 of the uart control register (address 001b 16 ) is ?? (n-channel open-drain output mode) n-channel open-drain output (note) 1 k w 100 pf measurement output pin switching characteristics 1 (v cc = 4.0 to 5.5 v, v ss = 0 v, t a = C20 to 85 c, unless otherwise noted. notes 1 : when the p4 5 /t x d p-channel output disable bit of the uart control register (bit 4 of address 001b 16 ) is 0. 2 : x out and x cout pins are excluded. serial i/o clock output h pulse width serial i/o clock output l pulse width serial i/o output delay time (note 1) serial i/o output valid time (note 1) serial i/o clock output rising time serial i/o clock output falling time cmos output rising time (note 2) cmos output falling time (note 2) 140 30 30 30 30 symbol parameter limits min. ns ns ns ns ns ns ns ns unit t c(s clk ) /2C30 t c(s clk ) /2C30 C30 10 10 typ. max. t wh(s clk ) t wl(s clk ) t d(s clk Ct x d) t v(s clk Ct x d) t r(s clk ) t f(s clk ) t r(cmos) t f(cmos) extended operating temperature version : v cc = 3.0 to 5.5 v, t a = C40 to C20 c and v cc = 2.5 to 5.5 v, t a = C20 to 85 c) fig. 37 circuit for measuring output switching characteristics (1) switching characteristics 2 (v cc = 2.5 to 4.0 v, v ss = 0 v, t a = C20 to 85 c, unless otherwise noted. notes 1 : when the p4 5 /t x d p-channel output disable bit of the uart control register (bit 4 of address 001b 16 ) is 0. 2 : x out and x cout pins are excluded. extended operating temperature version : v cc = 3.0 to 5.5 v, t a = C40 to C20 c and v cc = 2.5 to 5.5 v, t a = C20 to 85 c) serial i/o clock output h pulse width serial i/o clock output l pulse width serial i/o output delay time (note 1) serial i/o output valid time (note 1) serial i/o clock output rising time serial i/o clock output falling time cmos output rising time (note 2) cmos output falling time (note 2) 350 50 50 50 50 symbol parameter limits min. ns ns ns ns ns ns ns ns unit t c(s clk ) /2C50 t c(s clk ) /2C50 C30 20 20 max. t wh(s clk ) t wl(s clk ) t d(s clk Ct x d) t v(s clk Ct x d) t r(s clk ) t f(s clk ) t r(cmos) t f(cmos) typ. 50 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3822 group timing diagram t w(reset) 0.8v cc 0.2v cc reset t c(x in ) t c(cntr) t wh(cntr) t wl(cntr) 0.8v cc 0.2v cc cntr 0 ,cntr 1 t wh(int) t wl(int) 0.8v cc 0.2v cc int 0 ?nt 3 t wh(x in ) t wl(x in ) 0.8v cc 0.2v cc x in t c(s clk ) t wl(s clk ) t wh(s clk ) 0.2v cc 0.8v cc s clk t r t f t d(s clk -t x d) t v(s clk -t x d) t x d r x d 0.2v cc 0.8v cc t su(r x d-s clk ) t h(s clk -r x d) ? 1998 mitsubishi electric corp. new publication, effective jan. 1998. specifications subject to change without notice. notes regarding these materials ? these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product best suited to the customers application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. ? mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-partys rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. ? all information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that customers contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. ? mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. ? the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these materials. ? if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. ? please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further details on these materials or the products contained therein. keep safety first in your circuit designs! ? mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. mitsubishi microcomputers 3822 group single-chip 8-bit cmos microcomputer rev. rev. no. date 1.0 first edition 980120 revision description list 3822 group data sheet (1/1) revision description |
Price & Availability of M38223E4-XXXGP
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |